A Simulation-Guided Paradigm for Logic Synthesis and Verification

This article proposes a new logic synthesis and verification paradigm based on circuit simulation. In this paradigm, high quality, expressive simulation patterns are pregenerated to be reused in multiple runs of optimization algorithms, resulting reduced time-consuming Boolean computations such as satisfiability (SAT) solving. Methods generate presented compared, bit-packing technique compress them is integrated into the implementation. The generated shown reusable across different algorithms after network function modifications. A algorithm, resubstitution, combinational equivalence checking, two examples using paradigm. simulation-guided used for efficient filtering choices, leading lower cost expanding search space. By adopting proposed we achieve 5.9% reduction number AIG nodes, compared 3.7% by state-of-the-art resubstitution within comparable runtime. SAT solver calls 9.5% with use accumulated earlier stages.